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Computer Architecture and Hardware Fundamentals

Core concepts of computer system architecture, CPU registers, memory hierarchies, buses, storage technologies, and hardware logic.

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Von Neumann Architecture
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1
Von Neumann Architecture
A computer design architecture where CPU instructions and data share the same physical memory space and bus system.
2
Harvard Architecture
A computer architecture that uses physically separate storage and signal pathways for instructions and data.
3
Arithmetic Logic Unit (ALU)
The digital circuit inside the CPU that performs arithmetic computations (addition, subtraction) and logical bitwise operations (AND, OR, NOT).
4
Program Counter (PC)
A processor register that holds the memory address of the next sequential instruction to be fetched and executed.
5
Instruction Register (IR)
A dedicated CPU register that holds the binary machine instruction currently being decoded and executed.
6
Memory Address Register (MAR)
A register that stores the memory location currently being read from or written to over the system address bus.
7
L1, L2, and L3 CPU Caches
A hierarchy of small, extremely fast SRAM on or near the processor die designed to reduce average memory access latency.
8
Volatile vs. Non-Volatile Memory
Volatile memory (like RAM) loses stored state when power is lost; non-volatile memory (like ROM, NAND flash) retains data indefinitely without power.
9
SRAM vs. DRAM
SRAM uses bistable flip-flops (4-6 transistors per bit) and needs no refresh; DRAM uses a capacitor and transistor per bit, requiring periodic electrical refresh cycles.
10
ROM (Read-Only Memory)
Non-volatile storage that retains permanent firmware instructions (such as the initial bootloader) even after the computer is turned off.
11
Flash Memory (NAND vs. NOR)
NAND flash offers high density and rapid write speeds for mass storage (SSDs); NOR flash allows byte-level random access for direct execution.
12
Motherboard Chipset: Northbridge and Southbridge
Traditional architecture where the Northbridge handles high-speed communication (CPU, RAM, PCIe GPU) and Southbridge manages slower I/O peripherals and storage.
13
PCIe (Peripheral Component Interconnect Express)
A high-speed serial point-to-point computer expansion bus standard using differential signaling across dedicated transmit/receive lanes.
14
RISC vs. CISC Architecture
RISC uses simple, fixed-length single-cycle instructions (e.g., ARM); CISC features complex, multi-clock instructions capable of direct memory operations (e.g., x86).
15
Instruction Pipelining
A processor implementation technique where multiple instruction execution stages (Fetch, Decode, Execute, Writeback) overlap concurrently.
16
Moore's Law
The empirical observation by Gordon Moore in 1965 that the number of transistors on an integrated circuit doubles approximately every two years.
17
Graphics Processing Unit (GPU)
A specialized electronic circuit composed of thousands of lightweight cores designed for highly parallel SIMD arithmetic and graphics rendering.
18
Direct Memory Access (DMA)
A hardware capability allowing peripheral sub-systems to transfer data directly to and from system RAM without routing through the main CPU.
19
Interrupt Request (IRQ)
A hardware signal sent by an external device to the CPU requesting immediate suspension of normal execution to handle a peripheral event.
20
Solid-State Drive (SSD) vs. HDD
SSDs use semiconductor flash memory with zero moving parts and near-instant seek times; HDDs rely on rotating magnetic platters and mechanical read/write heads.
21
NVMe (Non-Volatile Memory Express)
An open host controller interface specification designed specifically for accessing high-speed solid-state storage across the PCIe bus.
22
BIOS and UEFI
Firmware interfaces that initialize system hardware during power-on self-test (POST) and hand off control to the operating system bootloader.
23
System Bus Components
Composed of three logical buses: the Data Bus (transfers information), the Address Bus (selects memory locations), and the Control Bus (coordinates signals).
24
Thermal Throttling
An automatic processor safety mechanism that dynamically reduces clock frequency and voltage to prevent physical overheating when thermal thresholds are breached.

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