Technology, Computers and Digital Basics

Computer Architecture and Hardware

60 practice questions, each with the answer and an explanation.

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Random questions from this topic, one at a time. You see the answer and the explanation straight after each one.

All 60 questions

  1. In the classical Von Neumann computer architecture, which component is responsible for coordinating and directing the operations of all other hardware units by fetching and decoding instructions?
  2. Which internal CPU register holds the memory address of the next sequential instruction waiting to be fetched and executed?
  3. What type of high-speed semiconductor memory is built directly into or adjacent to the CPU core using static flip-flops to minimize latency when fetching recurring instructions?
  4. What maximum physical RAM address space can theoretically be directly addressed by a computer architecture possessing a 32-bit address bus?
  5. Which memory technology stores each bit of data in a tiny integrated capacitor that gradually loses charge and therefore requires periodic dynamic refreshing thousands of times per second?
  6. What hardware mechanism enables high-speed peripheral devices like network cards and storage drives to transfer data directly to and from system RAM without routing through the CPU?
  7. Which non-volatile firmware interface replaced the legacy BIOS (Basic Input/Output System) on modern personal computer motherboards, supporting faster boot times and drive partitions exceeding 2 terabā€¦
  8. What is the primary role of the Translation Lookaside Buffer (TLB) within a modern CPU's Memory Management Unit (MMU)?
  9. Which computer architecture approach emphasizes a small, highly optimized set of fixed-length instructions that typically execute in a single clock cycle?
  10. What optical storage medium utilizes a blue-violet laser with a wavelength of 405 nanometers to achieve significantly higher data density than a standard red-laser DVD?
  11. In solid-state storage (SSDs), what process is executed by the flash controller to evenly distribute write and erase cycles across all NAND flash blocks to avoid premature cell failure?
  12. What type of pipeline hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed execution in the pipeline?
  13. Which motherboard component historically managed high-speed communications between the CPU, RAM, and primary PCIe graphics slots before its functions were integrated directly into the CPU die?
  14. What is the standard pin battery model commonly installed on computer motherboards to power the CMOS volatile memory and real-time clock when the power supply is disconnected?
  15. Which high-speed protocol was designed specifically for solid-state storage to communicate directly over the PCI Express bus, bypassing legacy SATA controller bottlenecks?
  16. In computer arithmetic, what representation method is universally employed by modern hardware processors to represent signed integers, allowing addition and subtraction to use the same logic circuitryā€¦
  17. What term describes the smallest addressable unit of data on a standard mechanical hard disk drive, historically formatted as 512 bytes and expanded to 4,096 bytes in Advanced Format drives?
  18. Which expansion card slot form factor provides the highest point-to-point bandwidth for dedicated graphics processing units (GPUs) on modern consumer motherboards?
  19. What metric measures the maximum thermal power generated by a CPU or GPU under maximum real-world workload, used by system designers to engineer adequate cooling systems?
  20. What is the primary function of the floating-point unit (FPU), historically packaged as a separate math coprocessor (such as the Intel 8087)?
  21. Which type of read-only memory (ROM) can be erased and reprogrammed using electrical voltage signals without exposure to ultraviolet light?
  22. What unit of data transmission represents a single complete character in ASCII encoding, consisting of 8 binary bits in modern computing systems?
  23. In superscalar processor design, what hardware technique allows the CPU to process instructions out of their original program sequence when operands are ready, while ensuring in-order retirement?
  24. Which computer bus connects the CPU directly to system memory (RAM), transferring the actual binary content of instructions and program variables?
  25. What microscopic electronic component acts as the foundational building block of modern digital computer processors, functioning as an electrical switch controlled by a gate voltage?
  26. What phenomenon occurs when software instructions cause the CPU to fetch and execute instructions across a conditional branch that turns out to be wrong, requiring the pipeline to be emptied?
  27. Which computer peripheral interface standard introduced reversible Type-C connectors and supports alternate modes for transmitting DisplayPort video and USB Power Delivery up to 240 watts?
  28. In high-performance gaming and graphics hardware, what specialized memory technology stacks DRAM dies vertically using Through-Silicon Vias (TSVs) to achieve extreme memory bandwidth?
  29. Which RAID (Redundant Array of Independent Disks) configuration provides block-level striping across three or more disks with distributed parity to withstand the failure of a single drive?
  30. What is the primary role of the Voltage Regulator Module (VRM) located on a modern computer motherboard surrounding the CPU socket?
  31. What term describes the smallest unit of digital storage, representing either a binary 0 or 1?
  32. In the standard IEEE 754 single-precision (32-bit) floating-point representation, how many bits are allocated to the sign, exponent, and mantissa (fraction), respectively?
  33. Which logic gate outputs a binary 1 if and only if both of its input operands are binary 1?
  34. Which logic gate is celebrated in digital circuit design as a 'universal gate' because any fundamental Boolean function can be implemented solely using combinations of this gate?
  35. What combinational digital logic circuit adds two 1-bit binary inputs ( and ) along with an incoming carry bit () to produce a sum bit and an outgoing carry bit?
  36. What digital circuit selects binary data from one of multiple input channels and routes it to a single output transmission line based on the state of select lines?
  37. What type of sequential circuit element is edge-triggered by a clock pulse to sample and store a single bit of binary state until the next clock transition?
  38. In computer memory hierarchy, what term describes the condition when requested data is successfully found in the CPU cache, avoiding a high-latency access to main RAM?
  39. Which cache replacement policy removes the memory block that has not been accessed for the longest period of time when allocating space for a new cache line?
  40. In cache memory design, what cache write policy immediately updates both the cache and the underlying main memory simultaneously whenever a processor write occurs?
  41. What term describes the memory locality principle where if a memory location is accessed, nearby memory locations are likely to be accessed soon (such as in sequential array loops)?
  42. What is the standard data block size transferred between main RAM and the CPU cache in modern x86 and ARM processors?
  43. What type of hardware interrupt is triggered by catastrophic system failures (such as bus parity errors or memory corruption) and cannot be ignored or masked by the CPU?
  44. What is the primary function of a heat pipe in modern CPU and GPU cooling heatsinks?
  45. Which serial communication bus is widely used on computer motherboards for low-speed communication with monitoring sensors, fan controllers, and memory SPD EEPROMs, using just two signal lines (SDA anā€¦
  46. In modern computer memory, what does 'DDR' stand for in DDR4 or DDR5 SDRAM?
  47. What term describes the intentional execution of a processor at clock frequencies higher than the manufacturer's certified factory specifications to boost processing performance?
  48. Which computer architecture concept allows a single physical processor core to appear as two logical cores to the operating system by sharing execution units while duplicating architectural register sā€¦
  49. What is the primary function of a graphics card's VRAM (Video RAM)?
  50. What standard character encoding scheme uses 7 binary bits to represent 128 distinct characters, including English letters, numerals, and control codes?
  51. Which computer component contains the physical quartz crystal oscillator that vibrates at a precise frequency to generate clock timing pulses for the system?
  52. What type of parity or check code is widely integrated into enterprise server RAM to detect and automatically correct single-bit memory errors caused by cosmic rays or electrical noise?
  53. What term describes the delay, measured in clock cycles, between a memory controller requesting data from a specific column in RAM and the data becoming available on the bus?
  54. Which video display connector carries purely analog video signals through a 15-pin D-subminiature connector, widely used on CRT and early LCD monitors?
  55. What is the primary role of the Translation Lookaside Buffer's counterpartā€”the Page Tableā€”in an operating system's virtual memory subsystem?
  56. In high-speed differential serial data transmission (such as PCIe, SATA, and USB 3.0), why are signal traces routed in closely spaced parallel pairs?
  57. What processor feature enables real-time dynamic hardware adjustments to CPU clock speed and core voltage based on system load, known as SpeedStep in Intel and Cool'n'Quiet in AMD?
  58. Which level of CPU cache is typically shared among all processor cores on a modern multi-core die, rather than being private to an individual core?
  59. What type of computer system architecture utilizes physically separated memory spaces and buses for instructions and data, preventing data writes from corrupting instruction code?
  60. What term describes the smallest physical storage unit that can be read or written in a NAND flash solid-state drive, typically sized between 4 KB and 16 KB?

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